Active matrix display devices

ABSTRACT

In an active matrix display device, such as AMLCD, having an array of pixels (P) addressed via sets of row and column conductors ( 14, 15 ) to which, respectively, selection and data signals are applied, each pixel comprises a plurality of sub pixels (P 1 -P 4 ) which each have an associated switch, for example a TFT, (T 1 -T 4 ) and which are addressed with data signals through a common switch (T 1 ) coupled to a column conductor ( 15 ). Addressing the sub pixels through a common switch reduces the effective capacitance of the column conductor. By appropriate control of the switches (T 1 -T 4 ) the pixels can be driven in a first mode in which the common switch (T 1 ) is operated to control the simultaneous addressing of the sub pixels (P 1 -P 4 ) with a data signal, for example, for a video display with full grey scale capability, and in a second mode in which the switches (T 1 -T 4 ) are controlled sequentially to allow different data signals to be applied to the individual sub pixels, for example, as required for a low power standby mode of operation with limited grey scale and color capability.

This application is a 371 of PCT/IB03/03974 Sep. 12, 2003

This invention relates to active matrix electro-optic display devicescomprising an array of pixels addressed via sets of address conductors,and particularly to active matrix liquid crystal display devices(AMLCDs). The invention is concerned more especially with active matrixdisplay device circuit arrangements and methods of operation foraddressing groups of two or more sub-pixels within the array.

Conventionally, AMLCDs comprise a row and column array of pixels whichare connected to, and addressed via, sets of row and column addressconductors. The pixels of one row are usually connected to the same rowaddress conductor while each pixel in the row is connected to arespective, and different, column address conductor. An example of sucha device, its method of operation, and its method of fabrication aredescribed in U.S. Pat. No. 5,130,829 to which reference is invited andwhose contents are incorporated herein.

Such display devices are widely used in a variety of products, includingfor example lap-top computers, PDAs and mobile phones and other portableelectronic equipment. Full colour display devices are now becoming morecommon in relatively small products such as mobile phones. Also, forportability, these products tend to rely on batteries for their power.

It is desirable for display devices intended for use in mobile phoneapplications and the like to have a very low power consumption in orderto conserve battery power. However, there is increasing interest inintegrating video functions into mobile devices which means that theymust also have good grey scale capability. It is difficult to satisfyboth of these requirements at the same time and therefore displaydevices have been proposed which can be operated in two different modes,a relatively high power, full grey scale, mode and a low power modewhich has reduced grey scale capability.

One technique for reducing the power consumption of the display deviceis to operate it in an 8 colour mode in which the red, green and bluepixels of the display device are driven to one of two states, a lightstate in which the light transmission, or reflection, of the pixel ishigh and a dark state in which the light transmission, or reflection, islow. This method of operating the display device offers a reduced powerconsumption because the circuitry, such as digital to analogueconverters, which is required to generate the drive voltages for thegrey scales can be put into an inactive, low power, state.

This low power operating mode can be extended to offer increased greyscale and colour capability by dividing the pixels of the display intosub pixels. These sub pixels can be given different areas, for example apixel may consist of two sub pixels one having an area A and a secondhaving an area 2A. By independently driving these sub pixels to the darkstate or the light state the display can be operated to produce 64colours and 4 grey levels with only a moderate increase in powerconsumption compared to the 8 colour operation.

Examples of AMLCDs using this area-ratio grey-scale sub-pixellationapproach are described, for example, in U.S. Pat. No. 6,335,778 B1 andU.S. 2002/0047822A1, whose contents are incorporated herein as referencematerial.

Dividing each pixel into a number of sub pixels raises the issue as tohow these additional sub pixels should be addressed. FIG. 1 illustratesone approach to addressing the additional sub pixels, similar to thekind of approach described in U.S. 2002/0047822A1, in which each subpixel, P1 to P4, of a pixel P is addressed in a similar way to aconventional pixel. A respective TFT (Thin Film Transistor) is connectedbetween each sub-pixel and a common, adjacent, column address conductor15 associated with column m of the array. Additional row addressconductors 14 are provided, making four in total, Row n to Row n+3, sothat each sub pixel can be separately addressed with drive voltagesapplied to the column conductor. Examples of the row addressingwaveforms required are shown in FIG. 1 a. The address period for thefour sub pixels is divided into four sections during each of which a rowselection signal is applied to a respective row address conductor toturn on the associated TFT and simultaneously a data voltage signal isapplied to the column address conductor charge the associated sub pixel.A disadvantage of this addressing technique is that the capacitance ofthe column conductor will be increased by both the capacitance of theadditional TFTs connected to it and the capacitance of the crossoverswith the additional row conductors. The increased capacitance leads toan increase in power consumption. Other problems, such as the need touse enlarged components in the column drive circuit can also arise.

It is an object of the present invention to provide improved circuitarrangements for the pixels, and methods of operating such, enablingaddressing of groups of two or more sub pixels. It is a further objectto provide circuit arrangements which are compatible with operation ofthe display device in a low power stand by mode with reduced colour andgrey-scale capability, for example 64 colours, and in a video mode witha full grey scale capability.

In accordance with an aspect of the present invention, there is providedan active matrix display device comprising an array of pixels, a set ofrow conductors through which rows of pixels are selected, a set ofcolumn conductors through which data signals are supplied to selectedpixels, each pixel comprising a plurality of sub pixels which sub pixelsare each associated with a respective switching transistor forcontrolling the supply of a data signal to the sub pixel, wherein theplurality of sub pixels of a pixel are coupled to a column conductorassociated with the pixel via a common switching transistor throughwhich data signals are supplied to the sub pixels, and wherein thedevice is operable in a first mode in which the plurality of sub-pixelsof a pixel are addressed simultaneously with a data signal and in asecond mode in which the sub pixels of a pixel are addressedindividually with respective data signals.

The manner in which the sub pixels are connected, with all the subpixels of a pixel being addressed via one TFT that is connected to thecolumn conductor, has the advantage that the capacitance of the columnaddress conductor is significantly reduced compared to the arrangementof FIG. 1. When the display device is operated in the video mode thiscommon TFT can be used to control the simultaneous charging of the subpixels. In the low power operating mode the additional TFTs associatedwith the sub pixels can be used to allow different data to be applied tothe sub pixels.

The sub pixels of a pixel may conveniently be connected in a serial orparallel manner.

For ease of controlling the switching transistors and enabling readilythe operation of the pixels in the first and second modes, the switchingtransistors associated with the sub pixels of a pixel are preferablyconnected to respective, different, row conductors.

The invention is particularly advantageous in relation to AMLCDs, inwhich the sub pixels comprise liquid crystal display elements, but maybe used in active matrix display devices using other kinds of displayelements, for example electrophoretic display elements.

These and other advantageous features in accordance with the presentinvention are illustrated specifically in embodiments of various anddifferent aspects of the invention now to be described, by way ofexample, with reference to the accompanying drawings, in which:—

FIG. 1 shows schematically a possible circuit of a typical pixel,comprising a plurality of sub pixels, in an AMLCD.

FIG. 1 a shows schematically example waveforms for operating the AMLCDof FIG. 1;

FIG. 2 shows schematically the circuit configuration of a typical pixel,comprising a plurality of sub pixels, in an embodiment of AMLCDaccording to the present invention;

FIG. 3 shows schematically the circuit configuration of a typical pixel,comprising a plurality of sub pixels, in another embodiment of AMLCDaccording to the present invention;

FIGS. 4 and 5 illustrate schematically waveforms used in the driving ofthe devices of FIGS. 2 and 3 respectively;

FIG. 6 shows schematically, and in highly simplified form, an AMLCDaccording to the invention;

FIG. 7 shows schematically the circuit configuration of part of thepixel array, comprising a plurality of pixels in adjacent rows andcolumns, in a further embodiment of AMLCD in accordance with the presentinvention; and

FIGS. 8 and 9 illustrate schematically waveforms used in the driving ofthe device of FIG. 7 and the effects on the pixels concerned in firstand second modes of operation.

The same reference numbers and symbols are used throughout the Figuresto denote the same or similar parts.

Referring to FIG. 2, there is shown a part of a first embodiment ofAMLCD in accordance with the invention, comprising a typical pixel Pconsisting of a plurality, in this case four, sub pixels, P1-P4, eachhaving an associated TFT switch, T1-T4.

The group of sub pixels constituting the pixel P are connected in aserial manner. Each sub pixel P1 to P4 is connected to the outputterminal of a respective TFT switch T1 to T4 with the input terminal ofthe TFT switches T2 to T4 being connected to the preceding sub pixel.The input of the TFT switch T1 associated with the first sub pixel, P1,is connected to the associated column conductor 15 associated withcolumn m of the array. Data voltage signals for each of the sub pixelsP1-P4 are supplied through this single column conductor and the TFT T1which for this purpose is common to all sub pixels P1-P4. Each TFTswitch T1-T4 has a separate switching control (gating) signal which issupplied via a respective, different row conductor 14, Row n-Row n+3, towhich its control (gate) electrode is connected.

In the second example embodiment illustrated in FIG. 3, the group of subpixels P1-P4 of the pixel P are connected in a parallel manner. Againeach sub pixel P1 to P4 is connected to the output terminal of aswitching TFT T1-T4 but in this case the input terminals of all TFTsexcept that associated with the first sub pixel P1 are connected to thefirst sub pixel, P1. As before each TFT has a separate control signalsupplied via a respective and different row conductor 14, Row n-Row n+3,to which its control (gate) electrode is connected. Again TFT T1 iscommon to all sub pixels P1-P4 in that they all receive their datasignals through this TFT.

In both example embodiments, the number of sub-pixels in each pixelgroup can, of course, be varied.

It will be appreciated that for each pixel only one TFT, the common TFT,is connected directly to the column conductor. Consequently, thecapacitance of the column conductor is considerably reduced comparedwith the known arrangement in which each sub pixel TFT is connected tothe column conductor.

Both of these pixel circuit configurations have the further advantagethat they can readily be addressed in the two modes which correspond tothe low power mode and video mode described previously.

In the low power mode of operation different video information must beis applied to each of the sub pixels. This is achieved by supplying theinformation in the form of data voltage signals sequentially to thecolumn conductor and by applying appropriate switching waveforms to therow conductors. The switching waveforms required by the two examplecircuits of FIGS. 2 and 3 are different and are illustrated in FIGS. 4and 5, respectively.

In the case of the first example embodiment of FIGS. 2 and 4, the subpixels P1-P4 are charged sequentially, starting with P4 and ending withP1. This is achieved by using the overlapping row addressing,(switching), pulses shown in FIG. 4 to control the TFTs T1-T4appropriately. Each of the TFTs T1-T4 is turned on for a periodcorresponding to that of the row addressing pulse on its associated rowconductor, Row n-Row n+3, allowing the signal present on the columnconductor to pass therethrough. As shown, the timings of the rowaddressing pulses applied to the row conductors Row n-Row n+3 are suchthat in a first part of a row address period, in which the sub pixels ofa row of pixels are all addressed, a data signal applied to the columnconductor and intended for sub pixel P4 is transferred through all theTFTs to that sub pixel (and all other sub pixels). At the end of thisfirst period, the TFT T4 is turned off and the data signal is stored onsub pixel P4. In a following period, a data signal intended for subpixel P3 is applied which is transferred through TFTs T1 to T3 to thatsub pixel and stored thereon at the termination of the row addressingpulse applied to Row n+2. The remaining sub pixels are addressed similarmanner in subsequent address intervals with sub pixel P1 being the lastto be addressed with its intended data signal. At the termination of therow addressing pulse applied to the row conductor Row n, therefore, eachsub pixel is charged according to its relevant data signal.

In the case of the second example embodiment of FIGS. 3 and 5, the TFTswitches T2 to T4 associated with all sub pixels apart from the firstare selected sequentially while the first TFT T1 is held in a conductingstate. Finally, the first sub pixel P1 is charged and then the first TFTT1 is turned off. The row addressing pulse applied to Row n lasts forsubstantially all the row address period so as to hold TFT switch T1 onin this period and allowing data signals to be passed to sub pixels P2,P3 and P4 in respective sub-intervals in is which the TFTs T2, T3 and T4are turned on, individually, by appropriate address pulses of theirassociated row conductors T2, T3 and T4, starting with TFT switch T4 inan initial period.

In the video mode of operation for both embodiments, the same drive,data, voltage signal is applied to all of the sub pixels P1 to P4. Thisis achieved by holding the associated row conductors, Rows n+1 to n+3,at a voltage which turns on the TFT switches T2 to T4. Row n is thendriven with conventional row selection waveforms, the row voltage beingswitched to a select (gating) voltage level in order to turn on the TFTswitch T1 connected to the column conductor and to charge all sub pixelsP1-P4 simultaneously, and then returned to a non-select voltage level inorder to turn off this TFT T1 and to isolate the sub pixels P1-P4 fromthe column electrode. The TFT switches T2 to T4 of all pixels in thearray can be simply held on for the duration of this operational mode.

With regard to both embodiments, the row address pulses applied to therow conductors and the data signals applied to the column conductors andsupplied by peripheral drive circuits in generally conventional manner.FIG. 6 shows schematically a display device according to the inventionand using pixels of the kind described above with reference to FIGS. 2and 3. The pixels P, each comprising a plurality of sub pixels, areorganised in rows and columns to form a display pixel array 30.Typically, there may be several hundred rows and columns of pixels. Thepixels P in the same row share the same row conductor, 35, each row ofpixels thus having four associated row conductors in the case of theabove described examples, while the pixels P in the same column sharethe same column conductor, 38. The pixels are driven by peripheral drivecircuitry comprising a row drive circuit 40 connected to the set of rowconductors 35 and a column drive circuit 42 connected to the set ofcolumn conductors 38, the row and column drive circuits being arrangedto provide the required row address pulses and data signals to the rowconductors and column conductor associated with a pixel as describedabove. In a respective row address period the pixels in one row are alladdressed at the same time, using common row address pulses applied totheir associated sub-set of row conductors 35 and appropriate datasignals applied to their respective column conductors 38. Each row ofpixels is addressed in sequence in a respective row address period in aframe period and repetitively addressed in similar manner in successiveframe periods. The operation of the row and column drive circuits 40 and42 is controlled and synchronised by a timing and control circuit 45 towhich is supplied a video signal VS containing video information fromwhich the data signals required for the sub pixels are derived. The rowdrive circuit 40 comprises a digital shift register type circuit similarto conventional row drive circuits but suitably modified so as toprovide in a row address period the necessary row address pulses to asub-set of row conductors Row n-Row n+3 when addressing a row of pixels,as described previously with reference to FIG. 4 or 5. Likewise,although generally similar to conventional column drive circuits, columndrive circuit 42 is appropriately modified to provide data signals toeach column conductor 38 in the manner required for the previouslydescribed operation of the pixels. In addition, the row and column drivecircuits are selectively controllable by the timing and control unit 45in response to a mode selection control signal MS applied thereto so asto switch the manner of operation of these circuits between thatrequired for a low power mode of operation of the pixels and thatrequired for a video mode of operation of the pixels as previouslydiscussed. The kind of modifications necessary to the row and columndrive circuits for these purposes will be apparent to the skilledperson.

As in conventional AMLCDs, the sets of address conductors 35 and 38, theTFTs T1-T4 of each pixel, and sub pixel electrodes defining the subpixels P1-P4 of each pixel are all carried on a first substrate, forexample of glass, which is spaced from a second substrate carrying acontinuous electrode common to all sub pixels in the array, with liquidcrystal disposed between the substrates. Using, for example, lowtemperature polysilicon thin film technology, the drive circuits 40 and42 are preferably integrated on the first substrate and fabricatedsimultaneously with the active matrix circuit of the pixels.

It is possible to reduce the number of row conductors required toaddress the display device by using a modified pixel circuit andmodified row addressing waveforms. An example of part of an array whichmakes use of the addressing scheme proposed here is shown in FIG. 7. Inthis example pixels X+1 and X+2, X+3 and X+4, X+5 and X+6 etc. representpairs of sub pixels in a display device which provides for a 64 colourlow power operating mode by dividing the area of each pixel into twoarea ratioed sub pixels.

Considering, for example, the pixel comprising sub pixels x+1 and x+2,the TFT T1 associated with sub pixel x+1 is controlled by row addressingpulses on row conductor Row n while the TFT T2 associated with the subpixel x+2 is controlled by row addressing pulses on the next rowconductor, Row n+1. The input of the TFT T2 is connected to the columnconductor Column m while the input of the TFT T1 is connected to theoutput of TFT T2, whereby a data signal for sub pixel x+2 is suppliedvia TFT T2 while a data signal for sub pixel x+1 is supplied via bothTFTs T2 and T1. The following pixel in the same column, comprising subpixels x+3 and x+4 is connected in a similar way with TFTs T3 and T4associated with sub pixel x+3 and x+4 respectively being controlled byrow address pulses on row conductors Row n+1 and Row n+2 and with theinput of TFT T4 being connected to column conductor Column m and theinput of TFT T3 being connected to the output of TFT T4. The remainingpixels in the same column are connected in similar manner. The pixels inother columns are arranged in corresponding manner, with the pixels ineach column being connected to a respective, and different columnconductor and with adjacent pairs of pixels each sharing a rowconductor.

In the low power mode where the sub pixels must be addressed withdifferent information, the array is scanned from top to bottom using therow addressing waveforms shown in FIG. 8 with the waveform labelled Rown being applied to row conductors Row n and so on. In order to addressthe sub pixels X+2, X+4, X+6, X+8 etc, the row conductor below the pixelmust be taken to a select level. In order to address the sub pixels X+1,X+3, X+5, X+7 etc. both the row conductor above and the row conductorbelow the pixel must be taken to the select voltage level.

Since taking one of the row conductors to the select voltage level willaffect both the row of pixels above and below the selected row conductorit is important that the rows are addressed in the correct sequence sothat information applied to a particular sub pixel is not corrupted whena subsequent sub pixel is being addressed.

FIG. 8 indicates the operations that are being performed on each of thesub pixels during each period of the addressing sequence. There arethree types of operation:

1) Charging, (labelled “Charge Pixels” in FIG. 8), when the sub pixel isconnected to the column conductor via the switching TFTs and is chargedto the voltage present on the column conductor.

2) Charge sharing, (labelled “Share Charge” in FIG. 8), when the TFTbetween a pair of the sub pixels is turned on and charge sharing takesplace between the capacitances of the sub pixels, the sub pixels beingisolated from the column conductor during this operation.

3) Holding, (labelled “Hold Voltage” in FIG. 8) when the voltage ismaintained on the capacitance of the sub pixels.

As shown in FIG. 8, in a first sub-period of the illustrated addressingcycle row address pulses are applied to row conductors Row n and Row n+1thereby turning on TFTs, T1, T2 and T3. At the same time a data signalvoltage intended for sub pixel x+1 is applied to the column conductorcolumn m, thus charging sub pixels x+1 and x+2. Because TFT T3 is alsoturned on in this sub-period, charge sharing occurs between sub pixelsx+3 and x+4. In the following sub-period, the row address pulse on rowconductor Row n only is maintained while a data signal intended for apreceding sub pixel x (not shown) is applied. During this sub-period thevoltages on sub-pixels x+1 and x+2 are held. In the next sub-period therow address pulse on Row n is removed and row address pulses applied toRow n+1 and Row n+2, with a data signal intended for sub pixel x+3applied to the column conductor. This results in the voltage on subpixel x+1 being held while the sub pixel x+2 is charged to this datasignal level. At the same time charging of sub pixels x+3 and x+4 takesplace while charge sharing between sub pixels x+5 and x+6 occurs. In thenext sub-period the row address pulse on Row n+2 is removed while therow address pulse on Row N+1 is maintained. In this sub-period a datasignal intended for sub pixel x+2 is applied to the column conductor.Thus, the voltage on sub pixel x+1 is still held while sub pixel x+2 ischarged to the data signal level, and the voltage on sub pixels x+3 andx+4 is merely held. In the following sub-period, in which a data signalintended for sub pixel x+5 is applied to the column conductor, theaddress pulse on Row n+1 is removed, and address pulses applied to Rown+2 and Row n+3. This results in the voltages on sub pixels x+1, x+2 andx+3 being held, the charging of sub pixels x+4, x+5 and x+6, and chargesharing between sub pixels x+7 and x+8.

This manner of operation continues, as depicted in FIG. 8, until all thesub pixels in the column have been charged according to their intendeddata signals.

While FIG. 8 shows the manner in which the pixels in one column areaddressed, it will be appreciated that the other columns of pixels areaddressed in a similar way and at the same time.

The sequence in which the sub pixels are addressed is chosen so thatafter a sub pixel has been charged to the required drive voltage level,according to the supplied data signal voltage, it will not undergo anyfurther charge sharing or charging operation until shortly before it isre-addressed in the following field period.

In the video operating mode the same video information must be appliedto pairs of sub pixels. This is achieved using the addressing waveformsshown in FIG. 9. In this mode, the display device must be scanned in thereverse direction, from bottom to top, in order to avoid disturbing thepixel voltage after it has been addressed. Thus in a first sub-period ofthe illustrated addressing cycle, row address pulses are applied to Rown+3 and Row n+4 while a data signal voltage for sub pixels x+7 and x+8is applied to the column conductor. Consequently, sub pixels x+6, x+7and x+8 are all charged to the level of this data signal while thevoltage on all other sub pixels in the column is held. In a followingsub-period, a data signal intended for sub pixels x+5 and x+6 is appliedand row address pulses applied only to Row n+3 and Row n+2, resulting inthe voltage on sub pixels x+7 and x+8 being held, and sub pixels x+4,x+5 and x+6 being charged to the applied data signal level. This mannerof operation continues, as depicted in FIG. 9, until all sub pixels havebeen addressed.

While described in relation to AMLCDs in particular, it is envisagedthat the invention may be applied to active matrix display devices usingelectro-optic materials other than LC material, for exampleelectrophoretic material.

In summary, therefore, active matrix display devices have been describedwhich have an array of pixels addressed via sets of row and columnconductors to which, respectively, selection and data signals areapplied, each pixel comprises a plurality of sub pixels which each havean associated switch, for example a TFT, (T1-T4) and which are addressedwith data signals through a common switch (T1) coupled to a columnconductor. Addressing the sub pixels through a common switch reduces theeffective capacitance of the column conductor.

By appropriate control of the switches (T1-T4) the pixels can be drivenin a first mode in which the common switch (T1) is operated to controlthe simultaneous addressing of the sub pixels (P1-P4) with a datasignal, for example, for a video display with full grey scalecapability, and in a second mode in which the switches (T1-T4) arecontrolled sequentially to allow different data signals to be applied tothe individual sub pixels, for example, as required for a low powerstandby mode of operation with limited grey scale and colour capability.

From reading the present disclosure, many other modifications will beapparent to persons skilled in the art. Such modifications may involveother features which are already known in the art and which may be usedinstead of or in addition to features already described herein.

1. An active matrix display device comprising: an array of pixels, a setof row conductors through which rows of pixels are selected, a set ofcolumn conductors through which data signals are supplied to selectedpixels, each pixel comprising a plurality of sub pixels in which subpixels are each associated with a respective switching transistor forcontrolling the supply of a data signal to the sub pixel, a timing andcontrol unit for controlling a row drive circuit and a column drivecircuit that provide driving signals and the data signals to the arrayof pixels, the timing and control unit selectively switching between afirst mode of operation and a second mode of operation in response to amode selection control signal, wherein the plurality of sub pixels of apixel are coupled to a column conductor associated with the pixel via acommon switching transistor through which data signals are supplied tothe sub pixels, and wherein the device is selectively operable in thefirst mode in which the plurality of sub-pixels of a pixel are addressedsimultaneously with a data signal and in the second mode in which thesub pixels of a pixel are addressed individually with respective datasignals.
 2. The display device according to claim 1, wherein the devicecomprises drive means for providing data signals to the columnconductors and switching signals to the row conductors, and wherein thedrive means is operable in the first mode to switch the switchingtransistors associated with the sub pixels of a pixel at the same timeso as to supply a data signal on the associated column conductor to eachsub pixel, and wherein the drive means is operable in the second mode toswitch the switching transistors associated with the sub pixels of thepixel selectively in sequence such that data signals on the associatedcolumn conductor are supplied to respective sub pixels.
 3. The displaydevice according to claim 1, wherein the sub pixels of a pixel areconnected in serial manner with the input terminal of the switchingtransistor associated with the first sub pixel of the series beingconnected to the associated column address conductor and with the inputterminal of the switching transistor associated with each of the othersub pixels in the series being connected to the output terminal of theswitching transistor associated with the preceding sub pixel in theseries.
 4. The display device according to claim 1, wherein the subpixels of a pixel are connected in parallel manner with the inputterminal of the switching transistor associated with one sub pixel beingconnected to the associated column address conductor and with the inputterminals of the switching transistors associated with the other subpixels being connected to the output terminal of the switchingtransistor associated with the one pixel.
 5. The display deviceaccording to claim 1, wherein the control electrodes of the switchingtransistors associated with the sub pixels of a pixel are connected torespective different row conductors.
 6. The display device according toclaim 1, wherein each pixel comprises first and second sub pixels,wherein the control electrodes of the switching transistors associatedwith the first and second sub pixels of a pixel are connected to firstand second row conductors respectively, wherein, for each pixel, theinput of the switching transistor associated with the first sub pixel isconnected to the associated column conductor and the input of theswitching transistor associated with the second sub pixel is connectedto the output of the switching transistor associated with the first subpixel, wherein the first row conductor connected to one pixel isconnected also to the control electrode of the switching transistorassociated with the second sub pixel of another pixel connected to theassociated column conductor, and wherein the second row conductorconnected to the one pixel is connected also to the control electrode ofthe switching transistor associated with the first sub pixel of afurther pixel connected to the associated column address conductor. 7.The display device according to claim 1, wherein the sub pixels compriseliquid crystal picture elements connected to the outputs of theirassociated switching transistor.
 8. The display device according toclaim 7, wherein at least two sub pixels of a pixel are of differentareas.
 9. The display device according to claim 1, wherein the commonswitching transistor corresponds to the respective switching transistorof one of the plurality of sub pixels.
 10. The display device accordingto claim 1, wherein each of the common switching transistor and therespective switching transistors comprise an input terminal, an outputterminal and a gate terminal, wherein the input terminal of the commonswitching transistor is connected to the column conductor associatedwith the pixel and the output terminal of the common switchingtransistor is connected to at least one of the input terminals of therespective switching transistors.
 11. The display device according toclaim 10, wherein the output terminal of the common switching transistoris connected to each of the input terminals of the respective switchingtransistors.
 12. The display device according to claim 10, wherein theoutput terminal of a first one of the respective switching transistorsis connected to the input terminal of a second one of the respectiveswitching transistors.
 13. The display device of claim 1, furthercomprising a timing and control unit, a row drive circuit and a columndrive circuit that are operable in the first mode to switch theswitching transistors associated with the sub pixels of a pixel at thesame time so as to supply a data signal on the associated columnconductor to each sub pixel, and wherein the timing and control unit,row drive circuit, and column drive circuit are operable in the secondmode to switch the switching transistors associated with the sub pixelsof the pixel selectively in sequence such that data signals on theassociated column conductor are supplied to respective sub pixels. 14.The display device of claim 1 in which each sub pixel corresponds to aswitching transistor and the switching transistor or transistors of apixel other than the common switching transistor are turned on duringthe first mode of operation for a period of time longer than that duringthe second mode of operation.
 15. The display device of claim 1, furthercomprising at least one digital-to-analog converter that provides a datasignal to the plurality of sub-pixels of the pixel when the displaydevice is operating in the first mode, and the at least onedigital-to-analog converter is turned off when the display device isoperating in the second mode.
 16. The display device of claim 1 in whichwhen the display device is operating in the first mode, the plurality ofsub-pixels of a pixel are addressed simultaneously with a data signalhaving a level selectable from a first number of levels, and when thedisplay device is operating in the second mode, the sub pixels of apixel are addressed individually with respective data signals eachhaving a level selectable from a second number of levels, the secondnumber being smaller than the first number.
 17. The display device ofclaim 16 in which the second number is equal to
 2. 18. An active matrixdevice comprising: a plurality of pixels, each pixel having at least twosub pixels; a plurality of column conductors and a plurality of rowconductors for addressing the pixels; a first row conductor thatcontrols a signal path between one of the pixels and one of the columnconductors, the first row conductor controlling a signal path betweentwo sub pixels of another pixel; a second row conductor that controls asignal path between the other pixel and one of the column conductors;and a timing and control unit for controlling a row drive circuit and acolumn drive circuit that provide driving signals and the data signalsto the plurality of pixels, the timing and control unit selectivelyswitching between a first mode of operation and a second mode ofoperation in response to a mode selection control signal.
 19. The activematrix device of claim 18, wherein the sub pixels of each pixel areratioed.
 20. The active matrix device of claim 19, wherein each pixelconsists of two ratioed sub pixels.
 21. An apparatus comprising: anarray of pixels in which each pixel comprises at least one pair of subpixels; column conductors each being connected to the pixels of onecolumn of the array of pixels; row conductors in which two or more ofthe row conductors are connected to the pixels of one row of the arrayof pixels, and some row conductors each being connected to two pixels inthe same column; and a display controller for providing data signals tothe column conductors and switching signals to the row conductors, thedisplay controller being selectively operable in a first mode to switchthe switching transistors associated with the sub pixels of a pixel atthe same time so as to supply a data signal on the associated columnconductor to each sub pixel, and the display controller beingselectively operable in a second mode to switch the switchingtransistors associated with the sub pixels of the pixel selectively insequence such that data signals on the associated column conductor aresupplied to respective sub pixels; wherein each of the pairs of subpixels is associated with a circuit for connecting to a column conductorand two row conductors, the circuit comprising: a first switchingtransistor with its input terminal connected to the column conductor,its output connected to the first sub pixel in the pair, and its controlterminal connected to the first row conductor; and a second switchingtransistor with its input terminal connected to the output terminal ofthe first switching transistor, its output terminal connected to thesecond sub pixel in the pair, and its control terminal connected to thesecond row conductor.
 22. The apparatus of claim 21, wherein at leasttwo sub pixels of a pixel are of different areas.
 23. The apparatus ofclaim 22, wherein the ratios of the areas of the sub pixels in a pixelare powers of two.
 24. A method comprising: driving a display device ina first mode in which a plurality of sub-pixels of each of an array ofpixels of the display device are addressed simultaneously with a datasignal; and driving a display device in a second mode in which the subpixels of each pixel are addressed individually with respective datasignals; using a timing and control unit to control a row drive circuitand a column drive circuit that provide driving signals and the datasignals to the array of pixels, the timing and control unit selectivelyswitching between the first mode and the second mode in response to amode selection control signal; wherein the display device comprises aset of row conductors through which rows of pixels are selected, a setof column conductors through which data signals are supplied to selectedpixels, and each sub pixel is associated with a respective switchingtransistor for controlling the supply of the data signal to the subpixel.
 25. The method of claim 24, further comprising selectivelyswitching between the first mode and the second mode in response to amode selection control signal.
 26. The method of claim 24 in whichdriving the display device in the first mode comprises: driving thevoltage on all row conductors connected to gate terminals of switchingtransistors associated with each sub pixel of a pixel to a voltage levelto turn on the switching transistors; driving the voltage on a columnconductor connected to the pixel to a level representing a data signal;and after the sub pixels of the pixel have been charged to a voltagecorresponding to the voltage on the column conductor, driving thevoltage on the row conductor connected to the gate terminal of a selecttransistor of the pixel to a voltage level to turn off the selecttransistor, wherein the select transistor is the only transistor in thepixel circuit that is directly connected to the column conductor. 27.The method of claim 26, wherein the data signal represents a grayscalevalue of a pixel in an image.
 28. The method of claim 26, wherein thedata signal represents a grayscale value of one color component of apixel in an image.
 29. The method of claim 26 in which driving thedisplay device in the first mode comprises maintaining the voltage onthe row conductor connected to the gate terminal or terminals ofswitching transistors other than the select transistor of the pixel at alevel that turns on the switching transistors after the voltage on therow conductor connected to the gate terminal of the select transistor ofthe pixel is driven to a level that turns off the select transistor. 30.The method of claim 24 in which driving the display device in the secondmode comprises: driving the voltage on a row conductor connected to agate terminal of a select transistor of a pixel to a voltage level toturn on the select transistor, wherein the select transistor is the onlytransistor in the pixel that is directly connected to the columnconductor; and for each sub pixel in the pixel: driving the voltage onrow conductors connected to switching transistors, if any, that arelocated between the column conductor and the sub pixel to a voltagelevel that turns on the switching transistors; driving the voltage on acolumn conductor connected to the pixel to a voltage level representinga light state or dark state for the sub pixel; and after the sub pixelhas been charged to a voltage corresponding to the voltage on the columnconductor, driving the voltage on the row conductor connected to theswitching transistor associated with the sub pixel to a voltage levelthat turns off the switching transistor.
 31. The method of claim 30,wherein the switching transistors of the target pixel are arranged inseries, and wherein driving the display device in the second modecomprises initially driving the voltage on all row conductors connectedto the target pixel to the logical on state and then driving thevoltages on the row conductors to the logical off state one rowconductor at a time as the sub pixels are charged in order from farthestfrom the column conductor to closest to the column conductor.
 32. Themethod of claim 30, wherein the select transistor is the switchingtransistor associated with one of the sub pixels and that sub pixel ischarged last.